The present invention relates to semiconductor devices such as complementary metal oxide semiconductor (CMOS) devices and metal oxide semiconductor field effect transistor (MOSFET) devices, and more particularly to a method for fabricating gates having notched features at the bottom of the gate by utilizing processing steps that significantly reduce the product cycle time.
As gate technology and particularly CMOS gate technology has advanced, the circuit elements of semiconductor devices have been designed to be smaller and more densely packed. One problem facing conventional gate technology is that lithographic masks used during the gate patterning process are incapable of forming very fine features.
Traditionally, a vertical sidewall has been an essential requirement for CMOS gates, which have been fabricated in the prior art by using a dry etch process such as reactive-ion etching (RIE). Relatively speaking, the merits of implementing a dry etch process are due mainly to its simplicity of controlling the plasmas and its result of producing more repeatable results than other processes, such as a wet etch method.
Many plasma parameters, for example, gas pressure, chemistry, and the source and biased power can be varied/modified during the dry etch process to obtain anisotropic plasmas in order to produce a gate with a vertical sidewall structure.
Although the above-mentioned methodology has been performed in this industry for a long time and has become somewhat standardized globalwide, it is expected to encounter tremendous difficulties in achieving a vertical gate sidewall in developing technologies, especially for the sub-0.05 micron semiconductor technology.
It is important for device performance reasons to fabricate a gate having substantially vertical sidewalls. This is because vertical gate sidewalls ensure a fixed physical width of the interface that is present between the gate and the underlying dielectric film. Good process control is thus needed for providing a vertical gate profile having a fixed interface width between the bottom portion of the gate and the underlying dielectric film.
One future problem facing the fabrication of sub-0.05 micron semiconductor devices is controlling the vertical gate sidewall profile using a conventional approach with an anisotropic plasma etch. For example, the vertical gate profile may have an enlarged footing at the base of the gate with the underlying gate dielectric being intact if the etch selectivity is too high, or the etch can vertically punch through the gate dielectric and damage the underlying semiconductor substrate if the etch selectivity is too low. The process difficulty is aggravated primarily by the requirement for a very thin underlying gate dielectric thickness, which is driven by attempting to advance the device electrical performance. As the desired gate electrical critical dimension has become smaller, the problem of punching through the underlying gate dielectric has worsened.
In view of the above drawbacks with prior art gate fabrication processes, there is a continued need for providing a new and improved method that is capable of fabricating a semiconductor device such as a CMOS or MOSFET in which the gate region of the device has a sub-0.05 micron gate electrical critical dimension.
One object of the present invention is to provide a method of fabricating a semiconductor device such as CMOS or MOSFET in which the gate region has a sub-0.05 micron electrical critical dimension.
A further object of the present invention is to provide a method of fabricating a semiconductor device in which the gate region has substantially vertical sidewalls associated therewith.
A yet further object of the present invention is to provide a method of fabricating a semiconductor device utilizing processing steps that are compatible with existing CMOS processing steps.
An even further object of the present invention is to provide a method of fabricating a semiconductor device wherein the vertical profile is sufficiently controlled so as to allow fabrication of a gate having an interface between the gate and the underlying gate dielectric that has a controlled physical width.
A still further object of the present invention is to provide a method of fabricating a semiconductor device in which the gate electrical critical dimension (CD) is substantially reduced so as to improve the performance of the device.
These and other objects and advantages are achieved in the present invention by fabricating gate regions that have a notched feature at the bottom portion of the gate. Moreover, the inventive method is capable of forming notched gates having an upper portion that has substantially vertical gate sidewalls. The height of the vertical gate sidewall is controllable by the inventive process so as to make the height higher or lower depending on the specific device requirement. The phrase xe2x80x9csubstantially vertical gate sidewallsxe2x80x9d as used herein denotes gate sidewalls that are essentially perpendicular to the substrate. In the present invention, substantially vertical sidewalls refer to gate sidewalls in the upper portion that have an angle from the substrate of greater than 88xc2x0, with angle of about 90xc2x0 being more preferred. Note that the substantially vertical gate sidewalls of the semiconductor devices of the present invention are present above the notched gate region.
Specifically, the method of the present invention, which is employed in fabricating the above-mentioned notched gate, comprises the steps of:
(a) forming a conductive layer on an insulating layer that is present on a surface of a semiconductor substrate;
(b) forming a mask on said conductive layer so as to at least protect a portion of said conductive layer;
(c) anisotropically etching said conductive layer not protected by said mask so as to thin said conductive layer to a predetermined thickness and to form a conductive feature underlying said mask, said conductive feature having substantially vertical sidewalls;
(d) forming a passivating layer at least on said substantially vertical sidewalls; and
(e) isotropically etching remaining conductive layer not protected by said mask to remove said predetermined thickness thereby exposing a lower portion of said conductive feature not containing said passivating layer, while simultaneously removing notched regions in said lower portion of said conductive feature.